Reduction of delta noise in coincidentcurrent magnetic matrix storage systems



March 1, 1966 Filed July 14. 1961 FIG.1

T. HORE REDUCTION OF DELTA NOISE IN GOINCIDENT-CURRENT MAGNETIC MATRIXSTORAGE SYSTEMS 4 Sheets-Sheet l INVENTOR TERENCE HORE March 1, 1966HQRE 3,238,516

T. REDUCTION OF DELTA NOISE IN COINCIDENT-CURRENT MAGNETIC MATRIXSTORAGE SYSTEMS Filed July 14. 1961 4 Sheets-Sheet 2 INVENTOR TERENCEHORE' AGENT March 1, 1966 T. HORE 3,238,516

REDUCTION OF DELTA NOISE IN COINCIDENT-CURRENT MAGNETIC MATRIX STORAGESYSTEMS 4 Sheets-Sheet 5 Filed July 14. 1961 INVENTOR TERENCE HOHE BYAGENT 3,238,516 ENT 4 Sheets-Sheet 4 NCIDENT-CURR SYSTEMS E N COI RAGET. HOR NOISE I TRIX ST R6 PR6 U gjvs i 1 as??? /RS7 s w h fi b i QM L ik i i i Wmmm wmwfiwm m m m INVENTOR TERENCE HORE AG ENT United StatesPatent C) 3,238,516 REDUCTION OF DELTA NOISE IN COINCIDENT- CURRENTMAGNETIC MATRIX STORAGE SYS- TEMS Terence Hore, Reigate, Surrey,England, assignor to North American Philips Company, Inc., New York,N.Y., a corporation of Delaware Filed July 14, 1961, Ser. No. 124,147Claims priority, application Great Britain, Aug. 23, 1960, 29,177/ 60 4Claims. (Cl. 340-174) This invention relates to coincident-currentmagnetic matrix storage systems.

The invention relates more particularly to magnetic matrix storagesystems of the type comprising a plurality of ferrite memory cores, eachof which has a substantially square hysteresis loop, the cores beingarranged in at least one plane in rows and columns; a plurality ofaddress wires, one for each row and one for each column, which threadall the cores in the respective row or column; an inhibit wire for eachplane which threads all the cores in the plane; an output wire whichthreads all the cores in such a manner as to minimize interference fromnonselected cores; means for selecting, when reading followed bywriting, a particular core by the application of a halfread-pulsefollowed by a half-write-pulse coincidentally to the two address wirescorresponding to the row and column of the particular core; and meansfor applying a half-inhibit-pulse to at least one inhibit Wire incoincidence with and in opposition to the half-read or the half-writepulses when it is required to inhibit reading or writing in a selectedcore.

Such a store is capable of storing binary information in the form of sand 1s and, when reading out from any given core of such a store, anoutput pulse can be made to appear on the output wire when a l is readand substantially no output when a 0 is read.

There are, however, a number of factors which can cause unwanted outputor noise. These will be further explained with reference to FIGURES land 2 of the accompanying drawings, in which:

FIG. 1 shows a typical hysteresis loop for a core of the tyne described;and

FIG. 2 shows an 8 X 8 memory matrix store containing the so-called worstpattern of information.

In FIGURE 1 P represents the position on the hysteresis loop of a corerecording a l and P that of a core recording a 0. HF represents themagnitude and direction of a write pulse which will cause a core to gofrom the point P or P to the point a and thence to the point P Ahalf-write pulse /2HF will act as a disturbance to cause the core to bedisplaced or disturbed to the points P11 or P01 and thence back to itsoriginal position. HF represents the magnitude and direction of a readpulse which will cause a core to go to the point and thence to PSimilarly /zHF represents a half-read pulse which will disturb a core tothe point P or P and thence back to its original position.

Every time that a half-pulse /2 HF or /2HF is applied to a core the corewill be disturbed and a small output pulse will occur on the outputwire. The output wire is normally threaded through the cores in such amanner that these small outputs from cores on the same same address wiresubstantially cancel each other. Such a winding is designated byreference numeral 3 in FIGURE 2 of the accompanying drawings andgenerally forms a diagonal pattern.

The magnitude of the disturb output from a core depends on its immediatepast history, i.e., how it was disturbed in the previous cycle, and willbe less if the disturb is in the same direction as the previous disturb.A core Patented Mar. 1, 1966 which has just been switched to a onestate, therefore, will give a large disturb when a half-read pulse /zHFis applied to it in the following cycle. A known solution to thisproblem is to apply at the end of a cycle a so called post-write disturbpulse in the read direction /zHF to all the cores of a plane by means ofthe inhibit wire designated reference numeral 4 in FIGURE 2. This pulseis also known as a half-inhibit pulse. Thus in the following cycle allthe cores will have the same immediate past history and the disturbnoise from applying a halfread pulse /2 HF will be reduced.

Referring to FIGURE 1 it can be seen, however, that the portion P Pwhich corresponds to half-reading a 1 core, is similar to but not quitethe same as the portion P P which corresponds to half-reading a 0 core.Thus in conditions where the out-put from a half-read 0 core has tocancel the output from. a half-read 1 core a small output pulse willoccur. These pulses are known as delta noise. This noise will be amaximum when the pattern of information is such that the output fromevery half-read 0 core is cancelled with an output from a half-read 1core, this situation being clearly the worst pattern. An example of thisworst pattern of information is shown in FIGURE 2, where if thedifference between a half-read O and a half-read 1 core is 5V, the deltanoise output from half-reading one of each of the address wires x and 3Will be 86V. If a half-pulse is applied to the inhibit wire all cores inthe plane will receive a half pulse and the delta noise output will be32 5V.

When using a plane with a larger number of, for example, 64 x 64, coresthe delta noise, in worst pattern conditions, from the post-writedisturb pulse will therefore tend to swamp the following read pulsesunless sufficient time is left for the delta noise pulse to decay. Alsowhen writing a 0 into a core, the delta noise from the half-inhibitpulse (inhibiting the Writing of a one) will tend to swamp thepost-write pulse itself. 'In addition, the length of the x wires and 3/wires (together called address wires) results in a large capacitybetween each of the address wires and the inhibit wire, which will tendto absorb current pulses.

It is an object of the present invention to mitigate or obviate thesedisadvantages and to provide a storage system capable of operatingsatisfactorily with a large number of, for example 64, cores in each rowand column.

The store according to the present invention comprises a plurality ofmagnetic cores arranged in at least one plane according to rows andcolumns; a plurality of address wires, one for each row and one for eachcolumn threaded through all the cores in the respective row or column;an inhibit wire for each plane threaded through all the cores in theplane; an output wire threaded through all the cores in such a manner asto minimize interference from non-selected cores; means for selecting,when reading followed by writing, a particular core by the applicationof a half-read pulse followed by a halfwrite pulse coincidentally to thetwo address wires corresponding to the row and column of the particularcore; means for applying a half-inhibit pulse to at least one inhibitwire in coincidence with and in opposition to the half-read or thehalf-write pulses when it is required to inhibit reading or writing in aselected core; and means for applying a half-read pulse to each of thesaid two address wires so as to be mutually non-coincident in time andprior to the half-read pulses.

An embodiment of the invention will now be described by way of examplewith reference to FIGURES 3-5 of the accompanying drawings in which:

FIGURE 3 shows a number of planes of cores of the type herein set fortharranged in a stack;

FIGURE 4 shows a number of waveforms occurring during the operation ofthe storage;

FIGURE 5 shows a selection system for selecting an address wire.

FIGURE 3 shows a number of planes of cores in which each plane of coresis of the type set forth above and arranged substantially as shown inFIGURE 2 except that there are 64 x 64 cores in each plane. There are 64x address wires each of which is threaded through all the cores of therelevant row in each plane, and 64 y address wires each of which isthreaded through all the cores of the relevant column in each plane. Ofthese wires only one for each row and for a column is shown in FIG- URE3. Each plane, of which there are 20, has its own inhibit wire and anoutput wire is threaded through all the cores of every plane. When aselected core goes through the cycle of being read-out followed by beingwritten-in, the pulses shown in FIGURES 4 (a) and (b) are applied to therelevant x address wire and y address wire. For the reasons previouslygiven and in accordance with the invention a preread disturb pulse isapplied to each address wire. In the FIGURES 4a and 4b this is the shortpulse before the longer half-read pulse. It is necessary, of course,that the pre-read disturb pulse applied to the relevant x address wireand the relevant y address Wire should be mutually non-coincident intime since otherwise they would switch the core, which is not wanted.

The voltage induced in the output wire depends on whether a or 1 hasbeen stored in the core. The Waveform R corresponds to a 0, the waveformR to a 1 (FIG. 40). The waveform may be strobed to enable the voltageduring only the required time (referred to as the read-time) to beascertained, but this is not always necessary. Current will be appliedto the inhibit wires of all planes except one in coincidence with thehalf-read pulses in the x and y address wires in order to inhibitreading of a core in a non-desired plane. These pulses also preventinformation from being written back into the cores that have not beenread-out. When the writing of a one is inhibited by the application of ahalf-inhibit pulse to the inhibit wire' a large amount of delta noise iscaused in the output wire, the noise having a peak W at the start of thewrite pulse and a peak Wop at the end of the pulse as shown in FIGURE4c. As can be seen the peak W would tend to swamp a post-write disturbpulse if it were to be applied immediately after the half pulse forwriting, i.e., 8 sec. after start read time.

The relevant x address wire may be selected by means of a coordinateselection system as shown in FIGURE 5 and the relevant y address wiremay be selected by a similar coordinate selection system.

The coordinate selection system shown in FIGURE 5 selects any one of the64 address wires (i, j) (i, i=1, 2 8) (shown as thick lines) by means ofprimary and secondary selectors. Any one of the 64 addresses is selectedby selecting a particular one of 8 primary selectors and a particularone of 8 secondary selectors. The arrangement in FIGURE 5 comprises 8primary selectors RP for reading, 8 secondary selectors R5,' forreading, 8 primary selectors WP for writing and 8 secondary selectors WSfor writing. Each of these selectors is constituted by a transistorwhich is biased on or 011 by applying a voltage to its base. Thus whenit is required to select a particular address wire, for example, theaddress wire (2.4) for reading, the primary read selector RP .and thesecondary read selector RS are both biased on,

so forming a path for a read current, generated by a read currentgenerator RGen., through the relevant address wire 2.4. In a similarmanner a pulse may be applied to any address wire for writing by meansof the Write current generator WGen.

A pre-read disturb generator PRGen. is connected in parallel with theread current generator RGen. so that a pre-read disturb pulse may beapplied to an address wire selected in the manner described.

Many modifications of the invention will be apparent to those skilled inthe art without departing from the inventive concept, the scope of whichis set forth in the appended claims.

What is claimed is: V

1. A coincident current magnetic matrix system comprising a plurality offerrite memory cores, each of which has a substantially squarehysteresis loop, the cores being arranged in one plane in rows andcolumns; a plurality of address wires, one for each row and one for eachcolumn threading all the cores in the respective row or column; aninhibit wire for the plane threading all the cores in the plane; anoutput wire threading all the cores in such a manner as to minimizeinterference from half selected cores; means for selecting a particularcore, for reading followed by writing, by the application of a half-readpulse coincidentally to the two address wires corresponding to the rowand column of the particular core followed by the application of ahalf-write pulse coincidentally to the two address wires correspondingto the row and column of the particular core; means for applying ahalf-inhibit pulse to the inhibit wire in coincidence with and inopposition to the half-read or the half-write pulses when it is requiredto inhibit reading or writing-in a selected core; and means for applyingan additional half-read pulse to each of the said two address wiresprior to the application of the half-read pulse, said additionalhalf-read pulses being mutually non-coincident in time.

2. A coincident current magnetic matrixsystem as claimed in claim 1 inwhich the plane has sixty-four rows and sixty-four columns.

3. A coincident current magnetic matrix system comprising a plurality offerrite memory cores, each of which has a substantially squarehysteresis loop, the cores beingarranged in a plurality of planes inrows and columns within each plane; a plurality of address wires, onefor each row and one for each column, threading all the cores in therespective row or column; an inhibit wire for each plane threading allthe cores in the plane; an output wire threading al the cores in such amanner as to minimize interference from half selected cores; means forselecting a particular core, for reading followed by writing, by theapplication of a half-read pulse coincidentally to the two address wirescorresponding to the row, and column. of the particular core followed bythe application of a half-write pulse coincidentally to the two addresswires corresponding to the row and column of the particular core; meansfor applying a half-inhibit pulse to at least one inhibit wire incoincidence with and in opposition to the half-read or the half-writepulses when it is required to inhibit reading or writing in a selectedcore; and means for applying an aditional halfread pulse to each of thesaid two address wires prior to the application of the half-read pulse,said additional halfread pulses being mutually non-coincident in time.

4. A coincident current magnetic matrix system as claimed in claim 3 inwhich each plane has sixty-four rows and sixty-four columns.

References Cited by the Examiner UNITED STATES PATENTS 2,889,540 6/1959Bauer '340 '174 2,929,050 3/1960 Russell 340l74 2,970,296 1/1961 Horton340174 2,981,931 4/1961 Tate.

3,058,096 10/1962 Humphrey 340 174 X IRVING L. SRAGOW, Primary Examiner,

1. A COINCIDENT CURRENT MAGNETIC MATRIX SYSTEM COMPRISING A PLURALITY OFFERRITE MEMORY CORES, EACH OF WHICH HAS A SUBSTANTIALLY SQUAREHYSTERESIS LOOP, THE CORES BEING ARRANGED IN ONE PLANE IN ROWS ANDCOLUMNS; A PLURALITY OF ADDRESS WIRES, ONE FOR EACH ROW AND ONE FOR EACHCOLUMN THREADING ALL THE CORES IN THE RESPECTIVE ROW OR COLUMN; ANINHIBIT WIRE FOR THE PLANE THREADING ALL THE CORES IN THE PLANE; ANOUTPUT WIRE THREADING ALL THE CORES IN SUCH A MANNER AS TO MINIMIZEINTERFERENCE FROM HALF SELECTED CORES; MEANS FOR SELECTING A PARTICULARCORE, FOR READING FOLLOWED BY WRITING, BY THE APPLICATION OF A HALF-READPULSE COINCIDENTALLY TO THE TWO ADDRESS WIRES CORRESPONDING TO THE ROWAND COLUMN OF THE PARTICULAR CORE FOLLOWED BY THE APPLICATION OF AHALF-WRITE PULSE COINCIDENTALLY TO THE TWO ADDRESS WIRE CORRESPONDING TOTHE ROW AND COLUMN OF THE PARTICULAR CORE; MEANS FOR APPLYING AHALF-INHIBIT PULSE OF THE INHIBIT WIRE IN COINCIDENCE WITH AND INOPPOSITION TO THE HALF-READ OR THE HALF-WRITE PULSES WHEN IT IS REQUIREDTO INHIBIT READING OR WRITING-IN A SELECTED CORE; AND MEANS FOR APPLYINGAN ADDITIONAL HALF-READ PULSE TO EACH OF THE SAID TWO ADDRESS WIRESPRIOR TO THE APPLICATION OF THE HALF-READ PULSE, SAID ADDITIONALHALF-READ PULSES BEING MUTUALLY NON-COINCIDENT IN TIME.